Efficient k -Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning

A novel <em>k</em>-winners-take-all (<em>k</em>-WTA) competitive learning (CL) hardware architecture is presented for on-chip learning in this paper. The architecture is based on an efficient pipeline allowing <em>k</em>-WTA competition processes associated with different training vectors to be performed concurrently. The pipeline architecture employs a novel codeword swapping scheme so that neurons failing the competition for a training vector are immediately available for the competitions for the subsequent training vectors. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for realtime on-chip learning. Experimental results show that the SOPC has significantly lower training time than that of other <em>k</em>-WTA CL counterparts operating with or without hardware support.

Abstract licence: CC BY

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