A fast verification method of on-chip coupling interference based on VSDP-XcitePI

This paper describes a fast verification full-chain co-simulation flow based on the VSDP-XcitePI for extracting on-chip power supply models and simulating the effects of on-chip coupling interference. With this flow, XcitePI extracts the RLCK model or S-parameter model for metal layers of on-die power network and signals. This chip-level model together with package model was used in creating a new system-aware test bench to analyze the digital-to-analog interference in a RF AFE IC. The simulation results match well with the test phenomenon. Chip area of the IC used in analysis is 1.44 mm2, the analysis accuracy could support 10 μV variation，and the analysis bandwidth exceeds 5 GHz. In addition. This paper also introduces the flexible S-parameter post-processing flow inside VSDP platform, which ensures the convergence and high efficiency for the full-chain simulation.

Abstract licence: CC BY-NC

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