Below 100-fs Timing Jitter Seamless Operations in 10-GSample/s 3-bit Photonic Analog-to-Digital Conversion

We experimentally realize seamless operations with below 100-fs timing jitter in a 10-GSample/s 3-bit photonic analog-to-digital converter (ADC) with an input 2.5-GHz sinusoidal electrical signal. To address the energy efficiency, it is necessary to explore some serial approaches to get most operations in a photonic ADC done before serial-to-parallel conversion to save the number of devices. To press forward with the work on subsequent operations after optical sampling in a photonic ADC, we have investigated optical quantization and coding and demonstrated their performances. The experimental results successfully demonstrated seamless operations in a photonic ADC, i.e., sampling, quantization, and coding, while keeping its parallel-configuration-free characteristics and low timing jitter below 100 fs. This demonstration could address the energy efficiency by reduction of the number of devices, including electrical ADCs for subsequent operations after optical sampling in existing high-performance photonic ADCs.

Abstract licence: CC BY-NC-ND

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