A 1200-V-Class Ultra-Low Specific On-Resistance SiC Lateral MOSFET With Double Trench Gate and VLD Technique

An ultra-low specific on-resistance 4H-SiC power laterally diffused metal oxide semiconductor (LDMOS) device is proposed for 1200V-class applications. In the proposed SiC LDMOS device, a double-trench gate is introduced to reduce the channel region resistance. And a p-type variation lateral doping (VLD) region is also employed in the drift region, which not only optimizes the surface electric field and improves the breakdown voltage, but also increases the doping concentration of the N-drift region, resulting in a low drift region resistance. So that, the proposed device achieves an ultra-low specific on-resistance (<inline-formula> <tex-math notation="LaTeX">${R} _{\mathrm{ on,sp}}$ </tex-math></inline-formula>). Numerical Simulation results show that the <inline-formula> <tex-math notation="LaTeX">${R} _{\mathrm{ on,sp}}$ </tex-math></inline-formula> of the proposed SiC LDMOS is 3.5 <inline-formula> <tex-math notation="LaTeX">$\text{m}\boldsymbol{\Omega }\cdot {\mathrm{ cm}}^{2}$ </tex-math></inline-formula> with a breakdown voltage of &#x007E;1460V, which is reduced by more than 46&#x0025; compared with the conventional field-plate SiC LDMOS with a <inline-formula> <tex-math notation="LaTeX">${R} _{\mathrm{ on,sp}}$ </tex-math></inline-formula> of 6.6 <inline-formula> <tex-math notation="LaTeX">$\text{m}\boldsymbol{\Omega }\cdot {\mathrm{ cm}}^{2}$ </tex-math></inline-formula> and a breakdown voltage of &#x007E;1210V. The transconductance of the proposed device is improved greatly. And the trade-off relationship between the <inline-formula> <tex-math notation="LaTeX">${R} _{\mathrm{ on,sp}}$ </tex-math></inline-formula> and the breakdown voltage is also significantly improved compared with those of the conventional device and the previous literature.

Abstract licence: CC BY-NC-ND

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