Best Practices for Compact Modeling in Verilog-A
Colin C. McAndrew, Geoffrey J. Coram, Kiran K. Gullapalli and 8 more
IEEE Journal of the Electron Devices Society · 2015
doi:10.1109/jeds.2015.2455342 (opens in a new tab)
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Abstract
Verilog-A is the de facto standard language that the semiconductor industry uses to define compact models. Unfortunately, it is easy to write models poorly in Verilog-A, and this can lead to unphysical model behavior, poor convergence, and difficulty in understanding and maintaining model codes. This paper details best practices for writing compact models in Verilog-A, to try to help raise the quality of compact modeling throughout the industry.
Abstract licence: CC BY-NC-ND
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