Universal Equivalent Model for Real-Time CPU/FPGA Co-Simulation of Hybrid Cascaded Multilevel Converters

Real-time simulation is important for ensuring the reliable operation of VSC-HVDC converters in power grids, particularly through the use of rapid control prototyping (RCP) and hardware-in-the-loop (HIL) based converter controllers. While real-time simulation is a common practice for modular multilevel converters (MMCs), it has been less frequently applied to the new class of hybrid cascaded multilevel converters (HCMCs). In this study, a universal equivalent model (UEM) is proposed for a range of HCMC topologies that combines accuracy and computational efficiency through the use of both CPUs and field-programmable gate arrays (FPGAs). The proposed UEM is derived using the hybrid five-level converter (H5LC), a compact, efficient, and fault-tolerant VSC within the HCMC family. The UEM relies on CPUs to simulate the main circuits and controls of the main converter, and utilizes FPGAs to calculate the instantaneous voltages of a large number of full-bridge submodules (FBSMs), flying capacitors, and DC-side pole capacitors. In addition, the FBSMs’ voltage-balancing and switching algorithms are implemented on the FPGAs. The proposed real-time CPU/FPGA-based H5LC-UEM is compared to an offline CPU-based detailed equivalent model to verify its accuracy.

Abstract licence: CC BY-NC-ND

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