Design and Implementation of Asynchronous Processor on FPGA

Low-power and fault-tolerant features for microprocessors have been recognized as two of the greatest concerns in applications for edge devices. In this study, we propose asynchronous circuit design techniques for field-programmable gate arrays (FPGA) that can fundamentally overcome the drawbacks of conventional synchronous circuit designs. We used commercial FPGAs and implemented an asynchronous MSP430 microprocessor using the proposed technique. We also introduce an interfacing architecture between the synchronous block memory and asynchronous core to support the congeniality of the commercial embedded processor and the asynchronous core. Furthermore, we analyze a compiler for MSP430 and adapt its result to achieve a high-level development environment for asynchronous MSP430. The experimental results showed that the asynchronous MSP430 consumes 62.3% less power than its synchronous counterpart and has significant fault tolerance compared to the synchronous MSP430 under unstable supply voltage conditions. Additionally, the asynchronous MSP430 emitted 13% less electromagnetic noise at the working frequency.

Abstract licence: CC BY-NC-ND

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