Parallel-in encoding of quasi-cyclic low-density parity-check codes

Serial‐in encoders for quasi‐cyclic low‐density parity‐check (QC‐LDPC) codes are widely used. To provide flexible interfaces and reduce complexity, three parallel‐in QC‐LDPC encoders are proposed. One consists of shift‐register–adder–accumulator (SRAA) circuits, the others consist of rotate‐left‐accumulator (RLA) circuits. It is shown that a partially parallel‐in encoder is comparable to or even superior to a serial‐in one based on the same circuits; an RLA‐based encoder is preferable to a SRAA‐based one with the same speed, whether they are partially parallel‐in or fully parallel‐in.

Abstract licence: CC BY-ND

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