Stage-dependent minimum bit resolution maps of full-parallel pipelined FFT/IFFT architectures incorporated in real-time optical orthogonal frequency division multiplexing transceivers

Fast Fourier transform (FFT) and inverse FFT (IFFT) are the fundamental algorithms at the heart of optical orthogonal frequency division multiplexing (OOFDM) transceivers. The high digital signal processing (DSP) complexity has become one of the most significant obstacles to experimentally demonstrating real-time high-capacity OOFDM transceivers. In this study, extensive numerical explorations are undertaken, for the first time, of the impacts of each individual transceiver DSP element on the inverse error vector magnitude (IEVM) performance of the OOFDM transceivers incorporating full-parallel pipelined FFT/IFFT architectures. More importantly, FFT/IFFT stage-dependent minimum bit resolution maps are identified, based on which minimum bit resolutions of individual DSP elements of various FFT/IFFT stages can be easily selected according to chosen analogue-to-digital converter/digital-to-analogue converter resolutions. The validity and high accuracy of the identified maps are experimentally verified in field programmable gate array (FPGA)-based platforms. In addition to great ease of practical OOFDM transceiver designs, the maps also significantly reduce the FPGA logic resource usage without degrading the overall transceiver IEVM performance.

Abstract licence: CC BY-ND

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