SLIM: Simultaneous Logic-in-Memory Computing Exploiting Bilayer Analog OxRAM Devices

Abstract

von Neumann architecture based computers isolate computation and storage (i.e. data is shuttled between computation blocks (processor) and memory blocks). The to-and-fro movement of data leads to a fundamental limitation of modern computers, known as the Memory wall . Logic in-Memory (LIM)/In-Memory Computing (IMC) approaches aim to address this bottleneck by directly computing inside memory units thereby eliminating energy-intensive and time-consuming data movement. Several recent works in literature, propose realization of logic function(s) directly using arrays of emerging resistive memory devices (example- memristors, RRAM/ReRAM, PCM, CBRAM, OxRAM, STT-MRAM etc.), rather than using conventional transistors for computing. The logic/embedded-side of digital systems (like processors, micro-controllers) can greatly benefit from such LIM realizations. However, the pure storage-side of digital systems (example SSDs, enterprise storage etc.) will not benefit much from such LIM approaches as when memory arrays are used for logic they lose their core functionality of storage. Thus, there is the need for an approach complementary to existing LIM techniques, that’s more beneficial for the storage-side of digital systems; one that gives compute capability to memory arrays not at the cost of their existing stored states. Fundamentally, this would require memory nanodevice arrays that are capable of storing and computing simultaneously. In this paper, we propose a novel ‘Simultaneous Logic in-Memory’ (SLIM) methodology which is complementary to existing LIM approaches in literature. Through extensive experiments we demonstrate novel SLIM bitcells (1T-1R/2T-1R) comprising non-filamentary bilayer analog OxRAM devices with NMOS transistors. Proposed bitcells are capable of implementing both Memory and Logic operations simultaneously. Detailed programming scheme, array level implementation, and controller architecture are also proposed. Furthermore, to study the impact of proposed SLIM approach for real-world implementations, we performed analysis for two applications: (i) Sobel Edge Detection, and (ii) Binary Neural Network- Multi layer Perceptron (BNN-MLP). By performing all computations in SLIM bitcell array, huge Energy Delay Product (EDP) savings of ≈75× for 1T-1R (≈40× for 2T-1R) SLIM bitcell were observed for edge-detection application while EDP savings of ≈3.5× for 1T-1R (≈1.6× for 2T-1R) SLIM bitcell were observed for BNN-MLP application respectively, in comparison to conventional computing. EDP savings owing to reduction in data transfer between CPU ↔ memory is observed to be ≈780× (for both SLIM bitcells).

Full text

Its licence does not allow us to show the full text. Read it at PubMed Central:

References 38

1. 1.

   Wulf WA, McKee SA. Hitting the memory wall: implications of the obvious. ACM SIGARCH computer architecture news. 1995;23:20-24.

   Not in our library10.1145/216585.216588

2. 2.

   Horowitz, M. 1.1 computing’s energy problem (and what we can do about it). In Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International, 10–14 (IEEE, 2014).

   Not in our library

3. 3.

   Milojicic, D. et al. Computing in-memory, revisited. In 2018 IEEE 38th International Conference on Distributed Computing Systems (ICDCS), 1300–1309, 10.1109/ICDCS.2018.00130 (2018).

   Not in our library

4. 4.

   Hennessy, J. L. & Patterson, D. A. Computer architecture: a quantitative approach (Elsevier, 2011).

   Not in our library

5. 5.

   Chen Y-H, Krishna T, Emer JS, Sze V. Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks. IEEE Journal of Solid-State Circuits. 2017;52:127-138.

   Not in our library10.1109/jssc.2016.2616357

6. 6.

   Pawlowski, J. T. Hybrid memory cube (hmc). In 2011 IEEE Hot Chips 23 Symposium (HCS), 1–24 (IEEE, 2011).

   Not in our library

7. 7.

   Lee, D. U. et al. 25.2 a 1.2 v 8gb 8-channel 128gb/s high-bandwidth memory (hbm) stacked dram with effective microbump i/o test methods using 29 nm process and tsv. In Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International, 432–433 (IEEE, 2014).

   Not in our library

8. 8.

   Sze V, Chen Y-H, Yang T-J, Emer JS. Efficient processing of deep neural networks: A tutorial and survey. Proceedings of the IEEE. 2017;105:2295-2329.

   Not in our library10.1109/jproc.2017.2761740

9. 9.

   Wong H-SP, Salahuddin S. Memory leads the way to better computing. Nature nanotechnology. 2015;10:191.

   Not in our library10.1038/nnano.2015.29

10. 10.

    Linn E, Rosezin R, Tappertzhofen S, Böttger U, Waser R. Beyond von neumann—logic operations in passive crossbar arrays alongside memory operations. Nanotechnology. 2012;23:305205.

    Not in our library10.1088/0957-4484/23/30/305205

11. 11.

    You T, et al. Exploiting memristive bifeo3 bilayer structures for compact sequential logics. Advanced Functional Materials. 2014;24:3357-3365.

    Not in our library10.1002/adfm.201303365

12. 12.

    Gao S, et al. Implementation of complete boolean logic functions in single complementary resistive switch. Scientific reports. 2015;5:15467.

    Not in our library10.1038/srep15467

13. 13.

    Zhou Y, et al. 16 boolean logics in three steps with two anti-serially connected memristors. Applied Physics Letters. 2015;106:233502.

    Not in our library10.1063/1.4922344

14. 14.

    Kvatinsky S, et al. Magic—memristor-aided logic. IEEE Transactions on Circuits and Systems II: Express Briefs. 2014;61:895-899.

    Not in our library10.1109/tcsii.2014.2357292

15. 15.

    Wang Z-R, et al. Functionally complete boolean logic in 1t1r resistive random access memory. IEEE Electron Device Letters. 2017;38:179-182.

    Not in our library10.1109/led.2016.2645946

16. 16.

    Huang P, et al. Reconfigurable nonvolatile logic operations in resistance switching crossbar array for large-scale circuits. Advanced Materials. 2016;28:9758-9764.

    Not in our library10.1002/adma.201602418

17. 17.

    Sun Z, Ambrosi E, Bricalli A, Ielmini D. Logic computing with stateful neural networks of resistive switches. Advanced Materials. 2018;30:1802554.

    Not in our library10.1002/adma.201802554

18. 18.

    Kim KM, et al. Single-cell stateful logic using a dual-bit memristor. Physica status solidi (RRL)–Rapid Research Letters. 2019;13:1800629.

    Not in our library10.1002/pssr.201800629

19. 19.

    Seshadri, V. et al. Ambit: In-memory accelerator for bulk bitwise operations using commodity dram technology. In Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 273–287 (ACM, 2017).

    Not in our library

20. 20.

    Agrawal, A., Jaiswal, A., Lee, C. & Roy, K. X-sram: Enabling in-memory boolean computations in cmos static random access memories. IEEE Transactions on Circuits and Systems I: Regular Papers 1–14 (2018).

    Not in our library

21. 21.

    Sun, X., Liu, R., Peng, X. & Yu, S. Computing-in-memory with sram and rram for binary neural networks. In 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 1–4 (IEEE, 2018).

    Not in our library

22. 22.

    Zhou Y-X, et al. Nonvolatile reconfigurable sequential logic in a hfo 2 resistive random access memory array. Nanoscale. 2017;9:6649-6657.

    Not in our library10.1039/c7nr00934h

23. 23.

    Indiveri G, Liu S-C. Memory and information processing in neuromorphic systems. Proceedings of the IEEE. 2015;103:1379-1397.

    Not in our library10.1109/jproc.2015.2444094

24. 24.

    Wang, J., Park, D., Papakonstantinou, Y. & Swanson, S. Ssd in-storage computing for search engines. IEEE Transactions on Computers (2016).

    Not in our library

25. 25.

    Chang C-C, et al. Mitigating asymmetric nonlinear weight update effects in hardware neural network based on analog resistive synapse. IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 2018;8:116-124.

    Not in our library10.1109/jetcas.2017.2771529

26. 26.

    Chen, W.-H. et al. A 65 nm 1 mb nonvolatile computing-in-memory reram macro with sub-16ns multiply-and-accumulate for binary dnn ai edge processors. In 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 494–496 (IEEE, 2018).

    Not in our library

27. 27.

    Hong, X. et al. Oxide-based rram materials for neuromorphic computing. Journal of materials science 1–27 (2018).

    Not in our library

28. 28.

    Benoist, A. et al. 28 nm advanced cmos resistive ram solution as embedded non-volatile memory. In Reliability Physics Symposium, 2014 IEEE International, 2E–6 (IEEE, 2014).

    Not in our library

29. 29.

    Vasilakis, E. An instruction level energy characterization of arm processors. Foundation of Research and Technology Hellas, Inst. of Computer Science, Tech. Rep. FORTH-ICS/TR-450 (2015).

    Not in our library

30. 30.

    Maqsood T, et al. Leveraging on deep memory hierarchies to minimize energy consumption and data access latency on single-chip cloud computers. IEEE Transactions on Sustainable Computing. 2017;2:154-166.

    Not in our library10.1109/tsusc.2017.2706620

31. 31.

    IEEE. More Moore White Paper, IEEE IRDS, https://irds.ieee.org/images/files/pdf/2016_MM.pdf (2016).

    Not in our library

32. 32.

    Moons, B., Goetschalckx, K., Berckelaer, N. V. & Verhelst, M. Minimum energy quantized neural networks. In 2017 51st Asilomar Conference on Signals, Systems, and Computers (IEEE, 2017).

    Not in our library

33. 33.

    Liang S, Yin S, Liu L, Luk W, Wei S. FP-BNN: Binarized neural network on FPGA. Neurocomputing. 2018;275:1072-1086.

    Not in our library10.1016/j.neucom.2017.09.046

34. 34.

    Wu S-L, et al. A 0.5-v 28-nm 256-kb mini-array based 6t SRAM with vtrip-tracking write-assist. IEEE Transactions on Circuits and Systems I: Regular Papers. 2017;64:1791-1802.

    Not in our library10.1109/tcsi.2017.2681738

35. 35.

    Hsu, C.-W. et al. 3d vertical TaOx/TiO2 RRAM with over 103 self-rectifying ratio and sub-μa operating current. In 2013 IEEE International Electron Devices Meeting (IEEE, 2013).

    Not in our library

36. 36.

    Degraeve R, et al. Causes and consequences of the stochastic aspect of filamentary rram. Microelectronic Engineering. 2015;147:171-175.

    Not in our library10.1016/j.mee.2015.04.025

37. 37.

    Sassine, G. et al. Sub-pJ consumption and short latency time in RRAM arrays for high endurance applications. In 2018 IEEE International Reliability Physics Symposium (IRPS) (IEEE, 2018).

    Not in our library

38. 38.

    Hsu, C.-W. et al. Self-rectifying bipolar TaOx/TiO2 RRAM with superior endurance over 1012 cycles for 3D high-density storage-class memory. In 2013 Symposium on VLSI Technology, T166–T167 (IEEE, 2013).

    Not in our library

Cited by papers we hold 9

• Multiple bursts of speciation in Madagascar’s endangered lemurs · 2025
  Not checked
• Cerebral small vessel disease burden and longitudinal cognitive decline from age 73 to 82: the Lothian Birth Cohort 1936 · 2021
  Not checked
• Antimicrobial Resistance in Enterococcus Spp. Isolated from a Beef Processing Plant and Retail Ground Beef · 2021
  Not checked
• Gut microbiota link dietary fiber intake and short-chain fatty acid metabolism with eating behavior · 2021
  No notice
• Correlative 3D microscopy of single cells using super-resolution and scanning ion-conductance microscopy · 2021
  Not checked
• Multithreaded two-pass connected components labelling and particle analysis in ImageJ · 2021
  Not checked
• First description of a widespread Mytilus trossulus-derived bivalve transmissible cancer lineage in M. trossulus itself · 2021
  Not checked
• Aerosol tracer testing in Boeing 767 and 777 aircraft to simulate exposure potential of infectious aerosol such as SARS-CoV-2. · 2021
  Not checked
• Efficacy of corticosteroids in non-intensive care unit patients with COVID-19 pneumonia from the New York Metropolitan region. · 2020
  Not checked

Reads

A person counts once a day per paper. We keep no cookie and no address: a reader is a hash that changes every day. Any month under five reads shows no number.